The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device including a landing plug.
When performing a photolithography process using argon fluoride (ArF) having a wavelength of 193 nm in a semiconductor device having a line width of 80 nm or less, an additional condition has been generally required along with the typical etch process concepts, i.e., precise pattern formation and perpendicular etch profile. The condition refers to restraining deformation of photoresist which may be generated during etching. Thus, it has become important to develop an improved process condition which can satisfy typical conditions and the additional condition for restraining pattern deformation when fabricating a semiconductor of 80 nm or less. Meanwhile, various elements configuring a semiconductor device are formed into stack structures as the scale of integration accelerated. Thus, a contact plug (or a pad) is introduced. A landing plug contact technology using a self-aligned contact (SAC) method has been typically used when forming such contact plug. The landing plug contact technology is used to enlarge a contact surface area using a minimum surface area in a bottom portion, and to enlarge a process margin with respect to a subsequent process in an upper portion.
FIG. 1 illustrates a cross-sectional view of a typical method for fabricating a semiconductor device. Gate patterns G are formed over a substrate 11. Each gate pattern includes a stack structure configured with a gate insulation layer 12, a gate conductive layer 13 and a gate hard mask 14. An etch stop layer (not shown) is formed over the surface profile of the gate patterns G. An insulation layer is formed over the resultant structure. The insulation layer is planarized until the gate hard masks 14 are exposed. A photoresist pattern 17 is formed over a certain region of the planarized insulation layer. An anti-reflective coating layer 16 is formed between the photoresist pattern 17 and the planarized insulation layer. The planarized insulation layer is etched using the photoresist pattern 17 as an etch barrier to form contact holes 18 exposing the substrate 11 between adjacent gate patterns G. The process for forming the contact holes 18 is referred to as a self-aligned contact (SAC) etch process. Reference numeral 15 refers to a patterned insulation layer 15.
In the aforementioned typical method, the etch process for forming the contact holes 18 uses a gas including a CxFy gas comprising fluorine (F) and carbon (C), where x and y representing atomic ratios of C and F, respectively, range from approximately 1 to approximately 10, and a CaHbFc gas comprising C, hydrogen (H) and F, where a, b, and c representing atomic ratios of C, H, and F, respectively, range from approximately 1 to approximately 10. For example, the CaHbFc gas includes CH2F2.
However, a vertical height of gate patterns increases as the scale of integration increases. Thus, it may be inevitable to overly use an etch gas or increase an etch time during the SAC etch for an amount corresponding to the increased etch target. Consequently, etch losses ‘A’ may be generated in the gate hard masks 14, causing a decreased shoulder margin and inducing a contact hole not-open event ‘B’.
Prior arts for improving the aforementioned limitations are revealed in U.S. Pat. No. 6,174,451B1, U.S. Pat. No. 5,869,404B1, and U.S. Pat. No. 6,569,778B2, and U.S. Published Patent Application No. US20060003571 A1. However, it may be difficult to control complicated etch variables of the etch process in these prior arts because a CaHbFc gas or CxFy gas is added during the etch process.